1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device wherein the internal memory cell array and the peripheral circuit operate at a voltage lower than a power source voltage supplied from the outside and wherein a power source step-down circuit is provided for generating a voltage to be supplied to the memory cell array and the peripheral circuit.
2. Description of the Prior Art
In conventional SRAMs (static random access memories) of the CMOS (complementary metal oxide semiconductor) configuration, most of power source current upon waiting for circuit operation is consumed by an internal memory cell array. Current consumed by peripheral circuits other than the memory cell array such as an address decoder circuit and an operation controlling circuit is so low due to the low current consumption characteristic of the CMOS transistor itself that it can be ignored. For example, in an SRAM having a storage capacity of 1 Mbits, the current consumed by the entire memory cells for 1 Mbits is about 1 .mu.A, while the current consumed by the entire peripheral circuits upon waiting is about 0.05 .mu.A.
In recent years, as the fine working technique for VLSI (very large scale integration) advances, MOS transistors having a gate length of less than 0.5 .mu.m or so are employed for SRAMs having a storage capacity of 4 Mbits or so. However, when a MOS transistor having a gate length of less than 0.5 .mu.m or so is operated at the power source voltage of 5 V which is conventionally used, it is difficult to assure the reliability thereof against hot carriers. Therefore, an SRAM of the type mentioned is so constructed that a voltage step-down circuit is provided on a common semiconductor IC (integrated circuit) chip. The step-down circuit steps down the power source voltage of 5 V from the outside to an internal circuit voltage of, for example, 3.3 V, which is supplied to the internal circuits of the semiconductor memory device, that is, to the memory cell array and peripheral circuits.
FIG. 1 shows construction of a semiconductor memory device including a power source voltage step-down circuit. Referring to FIG. 1, peripheral circuit 7 and memory cell array 8 are interconnected by internal buses 9, and chip select terminal CS and address input terminals A.sub.0 to A.sub.n are connected to peripheral circuit 7. Internal circuit voltage V.sub.int is supplied from voltage step-down circuit 6a to peripheral circuit 7 and memory cell array 8.
Voltage step-down circuit 6a has power source voltage input terminal TC to which external power source voltage VCC is supplied, and includes constant-current source 1a, series diode circuit D1 including two diodes connected in series, a pair of operating amplifiers 3A and 3B, a pair of resistors R1 and R2 connected in series, and P-channel MOS transistor QP1 for providing a series controlling output. It is to be noted that, in the accompanying drawings, each P-channel MOS transistor is shown circumscribed by a circle, while each N-channel MOS transistor is shown without being circumscribed by a circle.
Constant-current source 1a is supplied with external power source voltage VCC by way of voltage input terminal TC and generates constant current I1a. Series diode circuit D1 is connected on the anode side thereof to constant-current source 1a by way of first node N1 and is grounded on the cathode side thereof. Consequently, series diode circuit D1 is supplied with constant current I1a and generates forward voltage 2 V.sub.f. Here V.sub.f is a forward voltage drop per one diode. Forward voltage 2 V.sub.f is supplied to the "+" terminal (positive input terminal) of first operational amplifier 3A. The output signal of first operational amplifier 3A, that is, reference voltage V.sub.ref, is divided by resistors R1 and R2 and is fed back to the "-" terminal (negative input terminal) of first operational amplifier 3A. Reference voltage V.sub.ref is also supplied to the "+" terminal of second operational amplifier 3B. The output of second operational amplifier 3B is connected to the gate of MOS transistor QP1, while the "-" input terminal of second operational amplifier 3B is connected to the drain of MOS transistor QP1. The source of MOS transistor QP1 is connected to power source input terminal TC so that the drain voltage of MOS transistor QP1 is supplied as internal circuit voltage V.sub.int to peripheral circuit 7 and memory cell array 8.
Internal circuit voltage V.sub.int, reference voltage V.sub.ref, forward voltage V.sub.f of each diode, and the resistances of resistors R1 and R2 have the relationship of V.sub.int =V.sub.ref =2 V.sub.f {(R1+R2)/R2}. Here, if it is assumed that, for example, V.sub.f =0.5 V, R1=2.3 k.OMEGA. and R2=1 k.OMEGA., then internal circuit voltage V.sub.int is equal to reference voltage V.sub.ref and is 3.3 V. While peripheral circuit 7 and memory cell array 8 are constituted from MOS transistors having a gate length of 0.5 .mu.m or so, since internal circuit voltage V.sub.int is, for example, 3.3 V and is sufficiently low, reliability against hot carriers can be assured.
Since a sufficiently high current driving capacity is required for P-channel MOS transistor QP1 to supply internal circuit voltage V.sub.int, P-channel MOS transistor QP1 is designed into a MOS transistor of the dimensions, for example, of a gate length of 1.0 .mu.m and a gate width of 1,000 .mu.m. Meanwhile, since external power source voltage VCC is applied as is to voltage step-down circuit 6a, the gate length of the MOS transistors employed in voltage step-down circuit 6a is designed greater than 0.8 .mu.m or so.
In power source voltage step-down circuit 6a, constant dc current I1a always flows through series diode circuit D1 in order to keep the potential at first node N1 equal to 2 V.sub.f. Further, in order to keep reference voltage V.sub.ref also at second node N2 at which first and second operational amplifiers 3A and 3B are connected to each other, dc current I2 always flows through resistors R1 and R2.
Here, the construction of constant-current source 1a is described with reference to FIG. 2. Constant-current source 1a is constituted from P-channel MOS transistor QP3, series diode circuit D2 including a pair of diodes connected in series, and resistor R3. The source of MOS transistor QP3 is connected to power source input terminal TC, while the drain of MOS transistor QP3 is connected to first node N1. The anode of series diode circuit D2 is connected to power source input terminal TC, and the cathode of series diode circuit D2 is connected to the gate of MOS transistor QP3. Resistor R3 is interposed between the gate of MOS transistor QP3 and the ground. The gate-source voltage of MOS transistor QP3 is made equal to forward voltage 2 V.sub.f of series diode circuit D2 so that the drain current of MOS transistor QP3 is kept to a fixed value and serves as a constant-current source. Also here, dc current I3 flows constantly through dc diode circuit D2 and resistor R3 in order to generate forward voltage 2 V.sub.f.
Exemplary construction of first operational amplifier 3A is shown in FIG. 3. Referring to FIG. 3, operational amplifier 3A is constituted as a known CMOS current mirror type amplifier circuit including a pair of P-channel MOS transistors QP13 and QP14 and three N-channel MOS transistors QN18 to QN20. MOS transistors QP13 and QP14 are connected at the sources thereof to power source input terminal TC and at the gates thereof commonly to the drain of P-channel MOS transistor QP13. The drains of N-channel MOS transistors QN18 and QN19 are connected to the drains of P-channel MOS transistors QP13 and QP14, respectively, and the sources of MOS transistors QN18 and QN19 are connected commonly and are grounded by way of a channel of MOS transistor QN20. Terminals a and b are connected to the gates of MOS transistors QN18 and QN19, respectively. Terminals a and b are the "+" input terminal and the "-" input terminal, respectively, of operational amplifier 3A. External power source voltage VCC is supplied to the gate of MOS transistor QN20. The drain of the other P-channel MOS transistor QP14 is connected to output terminal C.
In operational amplifier 3A, when the potentials at input terminals a and b are higher than ground potential GND by a voltage higher than the threshold voltage of the MOS transistors, steady current I4 exists which passes through MOS transistor QN20. Also, the other operational amplifier 3B has a similar construction to operational amplifier 3A and involves a steady current.
In power source voltage step-down circuit 6a of the conventional semiconductor memory device, steady currents I1a, I2, I3 and I4 always flow, and the total of the steady currents is 100 .mu.A or more, which is higher by two figures than the ordinary current consumption of the memory cell array.
Meanwhile, when a semiconductor memory device is constructing using a BiCMOS integrated circuit in which bipolar transistors and CMOS transistors are formed in a mixed condition, a data bus connected to a data sensing circuit is liable to have an increased length, and comparatively high parasitic capacitance CS is incidental to the data bus. Here, the data sensing circuit is a circuit provided for amplifying a data signal read out from each memory cell. In order to prevent a delay in operation after transition from the circuit waiting condition to the circuit operating condition arising from the presence of parasitic capacitance CS, a MOS transistor is provided through which bias current for keeping the potential of the data bus flows. While the MOS transistor is set so as to have a sufficiently small gate width, the bias current thereof is 1 mA or so, which is still higher than the steady currents I1a, I2, I3 and I4 described above.
As the storage capacity of a semiconductor memory device, particularly an SRAM, increases, the importance of defect analysis (analysis of causes of rejection) when the yield is decreased by various factors including fine leakage at memory cells and incomplete pattern formation progressively increases. In particular, in the defect analysis upon a decrease in yield, it is necessary to investigate various characteristics of the current consumed by the memory cell array, for example, the voltage characteristic, the temperature characteristic, the difference depending upon the write data of "0" and "1", and other factors. However, in the case of a semiconductor memory device having a power source voltage step-down circuit as described above, since a steady current higher than the current which is consumed by the memory cell array also flows through the voltage step-down circuit during waiting for circuit operation, even if the consumed current of the semiconductor memory circuit is measured simply, the current consumed by the memory cell array cannot be determined. Further, even if the power source voltage to be supplied from the outside is varied, the voltage actually applied to the memory cell array cannot be varied due to the presence of the voltage step-down circuit; consequently, the voltage characteristic of the memory cell array cannot be measured. Accordingly, it is very difficult to perform defect analysis upon decrease in yield.